As integrated circuit dimensions have moved progressively smaller, they are approaching a physical limit below which devices cannot be fabricated. Therefore, the traditional two-dimensional model of integrated circuits is undergoing a change towards three-dimensional integration. There are many challenges to overcome to make the progression to a three-dimensional paradigm. First, most integrated circuit fabrication techniques rely on modifying a wafer surface in some manner to form components and metallization paths. Therefore three-dimensional integration will likely rely on multiple stacked wafers with devices formed in each individual wafer.
Stacking multiple wafers presents many challenges. To adhere multiple wafers to one another, the wafers must be extremely flat to ensure wafer-to-wafer contact. Another challenge is interconnection among the devices positioned on various wafers. This requires vertical metallization to integrate devices positioned on different wafer.
U.S. Pat. No. 7,385,283 describes a method for making a three-dimensional integrated circuit. In this method, metal interconnects are aligned and a metal to metal bond formed during wafer stacking. At the same time, a non-metal to non-metal bond is formed between adjacent wafers. While this technique is one approach to vertical integration, the metallization of vias prior to wafer bonding can create problems during the wafer bonding process. If heat is used to bond the wafers, metal ions may diffuse into the wafer-to-wafer bonding region; for copper via metallization, diffused copper can “poison” nearby devices. For silicon wafers, copper doping forms deep level traps, seriously affecting the electrical properties of the overall 3-D stack. If chemical mechanical polishing is performed prior to the bonding, the metallization in the vias may not be even with the surface, resulting in difficulty forming a metal-to-metal bond between adjacent wafer vias and possible “shorts” between device levels. Further, the need to perform via metallization on each individual wafer followed by inter-wafer via bonding adds expensive and time-consuming processing steps to the overall process.
Thus there is a need in the art for improved techniques for vertical integration of wafers to form multi-layer integrated circuits.